The present invention generally relates to liquid crystal display panels and, more particularly to a driver for a liquid-crystal display panel, the driver having a reduced circuit area and power consumption and improving the picture quality of the liquid-crystal display panel.
To prolong the life of the liquid-crystal display panel, the driver has reversed the polarity of the picture voltage supplied to each pixel (picture element) cell of the liquid-crystal display panel (LCD panel).
FIG. 1 is a partial block circuit diagram of a data driver 11 for a conventional liquid-crystal display panel. The data driver 11 comprises a plurality of pairs of first and second digital-to-analog (D/A) converters 12 and 13, plural sets of output terminals P1, P2, P3, and P4, a plurality of pairs of polarity changeover switches 16 and 17, shift registers and latch circuits (neither are illustrated). The latch circuits latch digital picture signals supplied from external devices in accordance with latch control pulse signals from the shift registers.
A pair of the polarity changeover switches 16 and 17 are connected between the first and second D/A converters 12 and 13 and a pair of the output terminals, respectively. The changeover switch 16 selectively connects the output terminal of the first or second D/A converter 12 or 13 and the odd-numbered output terminal P1 (P3). The changeover switch 17 selectively connects the output terminal of the first or second D/A converter 12 or 13 and the even-numbered output terminal P2 (P4). Each of the polarity changeover switches 16 and 17 comprises first and second switches 18 and 19.
Each of the first and second D/A converters 12 and 13 comprises a selector 14 and an op amp 15. The selector 14 of the first D/A converter 12 receives the picture signal from the latch circuits as a first picture signal Vd1 (Vd3) and receives first gradation voltages Va1 to Va64. The selector 14 selects one of the first gradation voltages Va1 to Va64 in accordance with the first picture signal Vd1 (Vd3) and outputs the selection signal to the op amp 15. The op amp 15 outputs the selected voltage as a segment voltage. Thus, the first D/A converter 12 receives the first picture signal Vd1 (Vd3) and the first gradation voltages Va1 to Va64 and outputs a segment voltage (positive-polarity voltage) which is higher than a common voltage.
The selector 14 of the second D/A converter 13 receives the picture signal from the latch circuits as a second picture signal Vd2 (Vd4) and receives second gradation voltages Vb1 to Vb64. The selector 14 selects one of the second gradation voltages Vb1 to Vb64 in accordance with the second picture signal Vd2 (Vd4) and outputs the selected voltage to the op amp 15. The op amp 15 outputs the selected voltage as a segment voltage. Thus, the second D/A converter 13 receives the second picture signal Vd2 (Vd4) and the second gradation voltages Vb1 to Vb64 and outputs a segment voltage (negative-polarity voltage) which is lower than the common voltage.
The first switch 18 of the polarity changeover switch 16 is connected between the output terminal of the first D/A converter 12 and the odd-numbered output terminal P1 (P3). The first switch 18 of the polarity changeover switch 17 is connected between the output terminal of the second D/A converter 13 and the even-numbered output terminal P2 (P4).
The second switch 19 of the polarity changeover switch 16 is connected between the output terminal of the first D/A converter 12 and the even-numbered output terminal P2 or P4. The second switch 19 of the polarity change over switch 17 is connected between the output terminal of the second D/A converter 13 and the odd-numbered output terminal P1 or P3.
The first and second switches 18 and 19 complementarily turn on and off every one horizontal scanning period in response to a polarity switching signal FR. Accordingly, the positive-polarity segment voltage and the negative-polarity segment voltage are alternately supplied to each of the output terminals P1 to P4 every one horizontal scanning period.
For example, in response to the polarity switching signal FR, when the first switch 18 turns on and the second switch 19 turns off, the positive-polarity segment voltage from the first D/A converter 12 is applied to the odd-numbered output terminal P1 (P3) and the negative-polarity segment voltage from the second D/A converter 13 is applied to the even-numbered output terminal P2 (P4).
During the next horizontal period, when the first switch 18 turns off and the second switch 19 turns on, the positive-polarity segment voltage from the first D/A converter 12 is applied to the even-numbered output terminal P2 (P4) and the negative-polarity segment voltage from the second D/A converter 13 is applied to the odd-numbered output terminal P1 (P3).
The segment voltage applied to each output terminal is supplied to the pixel cell of the liquid-crystal display panel through a data line. The display level (brightness) of the pixel cell changes depending on the potential difference between the common voltage and a segment voltage Vs. Because the pixel cell comprises a liquid crystal cell and an auxiliary storage capacitor, the liquid-crystal display panel has a capacitive load on the data driver. Hence, the first D/A converter 12 charges the pixel cell through the data line and the second D/A converter 13 discharges a stored electric charge from the pixel cell through the data line. This charge/discharge operation increases the power consumption of the liquid crystal display panel as the number of horizontal pixel cells increases.
FIG. 2 is a partial block diagram of an improved data driver 21 for preventing the increase of power consumption. The data driver 21 comprises D/A converters 22 that correspond to the number of output terminals. Each of the D/A converters 22 comprises a selector 23 and an op amp 24, receives a picture signal Vd and gradation voltages V1 to V128, and alternately outputs the positive-polarity segment voltage Vs1 and the negative-polarity segment voltage Vs2. The gradation voltages V65 to V128 are positive-polarity segment voltages higher than the common voltage applied to each of the pixel cells, and the gradation voltages V1 to V64 are positive-polarity segment voltages lower than the common voltage. Accordingly, each of the D/A converters 13 alternately outputs one of the gradation voltages V65 to V128 and one of the graduation voltages V1 and V64 as the segment voltage Vs. During the same horizontal scanning period, the polarities of the gradation voltages selected by adjacent D/A converters 13 differ each other.
For example, as shown in FIG. 3a, the first D/A converter 22 alternately outputs a positive-polarity segment voltage Vsa and a negative-polarity segment voltage Vsb every one horizontal scanning period. The second D/A converter 23, adjacent to the first D/A converter 22, as shown in FIG. 3b, alternately outputs the negative-polarity segment voltage Vsb and the positive-polarity segment voltage Vsa every one horizontal scanning period.
Switches 25 are connected between the adjacent odd-numbered output terminal P1 (P3) and the even-numbered output terminal P2 (P4). Each of the switches 25 turns on for a predetermined period (for example, a retrace period which is a nonselective period of the pixel cell) in response to a control signal ER, and an electric charge moves from the data line charged to the positive-polarity voltage to the data line discharged to the negative-polarity voltage through the switches 25. In this case, the D/A converters 22 are maintained in the high impedance state. This charge/discharge allows the voltages of the data lines connected to the output terminals P1 to P4 to move to the vicinity of the common voltage. The D/A converters 22 are charged/discharged so as to change to a desired voltage from the common voltage. Because the charge/discharge operations of these converters 22 are performed centered around the common voltage, the power consumption is reduced.
However, the data driver 21 of FIG. 2 requires a signal generation circuit for generating the control signal ER of the switches 25, and so the circuit area of the data driver 21 is increased. The D/A converters 22 output the positive-polarity/negative-polarity segment voltage, and so they have about the same circuit area as the first and second D/A converters 12 and 13 of FIG. 1. This makes it difficult to increase the number of display pixels in a limited area.
FIG. 4 is a schematic block circuit diagram of another conventional data driver 111. The data driver 111 is equipped with a digital section 112 and the digital-to-analog (D/A) converters 22. The digital section 112 comprises latch circuits 114 and shift registers (not illustrated).
The shift registers sequentially transfer a latch control pulse signal and supply the latch control pulse signal to each of the latch circuits 114.
The latch circuits 114 correspond to the D/A converters 22. FIG. 4 shows only one of the latch circuits 114. Each of the latch circuits 114 latches a picture signal DD in accordance with the latch control pulse signal from the shift registers and supplies the latched signal to the corresponding D/A converter 22 as the picture signal Vd.
Each of the D/A converters 22 is connected to an external output terminal P. Accordingly, when the number of pixels of the liquid-crystal display panel increases, the number of D/A converters 22 increases and the circuit area of the data driver 111 increases.
FIG. 5 is a schematic block diagram of another conventional data driver 210. The data driver 210 is equipped with first to fourth digital-to-analog (D/A) converters 211 to 214, input switching circuits 215a and 215b, output switching circuits 216a and 216b, and shift registers and latch circuits (not illustrated). The adjacent first and second D/A converters 211 and 212 and the adjacent third and fourth D/A converters 213 and 214 form a pair, respectively.
The input switching circuit 215a receives n-bit picture signals D1n and D2n from the latch circuits. Then, in response to a polarity switching signal S1, the circuit 215a selectively outputs one of the picture signals D1n and D2n to the first D/A converter 211 and the other of the picture signals D1n and D2n to the second D/A converter 212.
The input switching circuit 215b receives n-bit picture signals D3n and D4n from the latch circuits. Then, in response to the polarity switching signal S1, the circuit 215b selectively outputs one of the picture signals D3n and D4n to the third D/A converter 213 and the other of the picture signals D3n and D4n to the fourth D/A converter 214.
The first D/A converter 211 selects the gradation voltage in accordance with the picture signal from the input switching circuit 215a and outputs the positive-polarity segment voltage Vs1 that is higher than the common voltage to the output switching circuit 216a.
The second D/A converter 212 selects the gradation voltage in accordance with the picture signal from the input switching circuit 215a and outputs the negative-polarity segment voltage Vs2 that is lower than the common voltage to the output switching circuit 216a.
The third D/A converter 213 selects the gradation voltage in accordance with the picture signal from the input switching circuit 215b and outputs a positive-polarity segment voltage Vs3 that is higher than the common voltage to the output switching circuit 216b.
The fourth D/A converter 214 selects the gradation voltage in accordance with the picture signal from the input switching circuit 215b and outputs a negative-polarity segment voltage Vs4 that is lower than the common voltage to the output switching circuit 216b.
The output switching circuit 216a, in accordance with the polarity switching signal S1, selectively outputs the positive-polarity voltage Vs1 from the first D/A converter 211 and the negative-polarity voltage Vs2 from the second D/A converter 212 to the output terminals P1 and P2.
The output switching circuit 216b, in accordance with the polarity switching signal S1, selectively outputs the positive-polarity voltage Vs3 from the third D/A converter 213 and the negative-polarity voltage Vs4 from the fourth D/A converter 214 to the output terminals P3 and P4.
FIG. 6 is a circuit diagram of an output switching circuit 216a. The output switching circuit 216a comprises four CMOS type transfer gates 217a to 217d and an inverter circuit 218.
The output terminal of the first D/A converter 211 is connected to the output terminals P1 and P2 through the transfer gates 217a and 217c. The output terminal of the second D/A converter 212 is connected to the output terminals P1 and P2 through the transfer gates 217b and 217d.
The NMOS transistor gates of the transfer gates 217a and 217d and the PMOS transistor gates of the transfer gates 217b and 217c receive the polarity switching signal S1. The PMOS transistor gates of the transfer gates 217a and 217d and the NMOS transistor gates of the transfer gates 217b and 217c receive the polarity switching signal S1 reversed by the inverter circuit 218. Because the output switching circuit 216b has the same configuration as the output switching circuit 216a, a detailed description thereof is omitted. Further, the input switching circuits 215a and 215b also have the same configuration as the output switching circuit 216a.
For example, as shown in FIG. 7, the input switching circuit 215a, in response to the polarity switching signal S1 having a H(high) level, supplies the picture signal D1n to the first D/A converter 211 and supplies the picture signal D2n to the second D/A converter 212. The transfer gates 217a and 217d of the output switching circuit 216a, in response to the polarity switching signal S1 having a H level, are conductively connected, and the transfer gates 217b and 217c are not conductively connected. Thus, the positive-polarity voltage Vs1 is supplied to the output terminal P1 through the transfer gate 217a and the negative-polarity voltage Vs2 is supplied to the output terminal P2 through the transfer gate 217d. The level of the polarity switching signal S1 is switched every one horizontal scanning period.
Further, as shown in FIG. 8, the input switching circuit 215a, in response to the polarity switching signal S1 having a L(low) level, supplies the picture signal D1n to the second D/A converter 212 and supplies the picture signal D2n to the first D/A converter 211. The input switching circuit 215b also operates in the same way as the input switching circuit 215a. The transfer gates 217b and 217c of the output switching circuit 216a, in response to the polarity switching signal S1 having a L level, are conductively connected and the transfer gates 217a and 217d are not conductively connected. Thus, the positive-polarity voltage Vs1 is supplied to the output terminal P2 through the transfer gate 217c, and the negative-polarity voltage Vs2 is supplied to the output terminal P1 through the transfer gate 217b.
As described above, the data driver 210 reverses the polarity of the picture voltage supplied to each pixel cell of the liquid-crystal display panel to prolong the life of each pixel cell. However, if the reverse operation of each pixel cell is delayed, a flicker may occur in the picture displayed on the liquid-crystal display panel. In particular, reversing the polarity of every pixel cell increases the brightness unevenness of every adjacent picture cell and, as a result, increases picture flickering.
It is an object of the present invention to provide a driver for liquid-crystal display panels with low power consumption.
A second object of the present invention is to provide a driver for liquid-crystal display panels with a reduced circuit area.
A third object of the present invention is to provide a driver for liquid-crystal display panels whose picture flickering is reduced.